PACT 2018
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Limassol, Cyprus
Nov 01-04, 2018

Dates & Deadlines:

  • April 8, 2018: Abstract Deadline
  • April 15, 2018: Paper Deadline
  • April 22, 2018: Workshop and Tutorial Proposal Deadline
  • June 4-6, 2018: Author Response Period
  • June 20, 2018: Author Notification
  • June 29, 2018: ACM Student Research Competition
  • July 9, 2018: Artifact Evaluation Submission Deadline
  • Aug 3, 2018: Camera Ready Final Papers
  • September 7, 2018: Student Travel Grants
  • November 01-04, 2018: PACT 2018

PACT 2018 Information:

Call for Contributions

Program

Location

Registration


PACT 2018 Organization:


Previous PACTs:
PACT17 PACT16 PACT15 PACT14 PACT13 PACT12 PACT11 PACT10 PACT09 PACT08 PACT07 PACT06 PACT05 PACT04 PACT03 PACT02 PACT01 PACT00 PACT99

Sponsors








Address questions to: skevos [at] cs.ucy.ac.cy

The 27th International Conference on
Parallel Architectures and Compilation Techniques (PACT18)
Limassol, Cyprus
November 01-04, 2018


Keynotes

Keynote speakers for PACT 2018:


"50 Years of Parallel programming: Ieri, Oggi, Domani*"
Keshav Pingali, Department of Computer Science and Institute for Computational Engineering and Science, The University of Texas at Austin

Thursday, November 1, 2018

Abstract
Parallel programming started in the mid-60's with the pioneering work of Karp and Miller, David Kuck, Jack Dennis and others, and as a discipline, it is now 50 years old. What have we learned in the past 50 years about parallel programming? What problems have we solved and what problems remain to be solved? What can young researchers learn from the successes and failures of our discipline? This talk is a personal point of view about these and other questions regarding the state of parallel programming.

*The subtitle of the talk is borrowed from the title of a screenplay by Alberto Moravia, and it is Italian for "Yesterday, Today, Tomorrow."

Biography
Keshav Pingali is a Professor in the Department of Computer Science at the University of Texas at Austin, and he holds the W.A."Tex" Moncrief Chair of Computing in the Institute for Computational Engineering and Sciences (ICES) at UT Austin.


"Quantum Computing - Vision and Reality"
Bettina Heim, Microsoft, Zurich, Switzerland

Friday, November 2, 2018

Abstract
Computing architectures have come a long way since the first universal transistor based computer almost 70 years ago. Society as we know it would not exist without access to the immensely powerful computing resources we have today. This begs the question of what technological innovations will shape our future over the next century. While the available computing power has scaled remarkably over the last couple of decades, it seems natural to question how far "traditional" architectures as they are in use today can evolve and whether there are any fundamental limitations to their power. Specializing hardware for a particular purpose may allow to circumvent or alleviate certain bottlenecks, and it seems natural to look for hardware that naturally behaves in a way that fits the problem to solve. One kind of hardware that has drawn a lot of attention lately are quantum computing devices. Where do these devises fit into the narrative on the evolution of computing devices? What kinds of problems do they strive to solve? What are the potential benefits and what developments yet need to happen for their widespread use? In my presentation I will talk about the ideas behind quantum computing, the current status quo, and why classical computing is a vital ingredient for building a quantum computer.

Biography
Bettina Heim is a quantum physicist and software developer in Microsoft's Quantum Architectures and Computation group. She is responsible for the Q# compiler and language design. Prior to joining Microsoft she worked on quantum algorithms, adiabatic quantum computing, discrete optimization problems, and the simulation and benchmarking of quantum computing devices.


"Architecting Chiplet-Based Systems"
Natalie Enright Jerger, Department of Electrical and Computer Engineering, University of Toronto, Canada

Saturday, November 3, 2018

Abstract
Moore´s law has conventionally enabled increasing integration; however, fundamental physical limitations have slowed the rate of transition from one technology node to the next, and the costs of new fabrication facilities are skyrocketing. Despite this, emerging applications such as machine learning have a seemingly insatiable appetite for more compute and memory bandwidth. The maturation of die stacking enables the continued integration of system components in traditionally incompatible processes. A key application of die-stacking is silicon interposer-based integration of multiple 3D stacks of DRAM, potentially providing several gigabytes of in-package memory. The use of an interposer presents new opportunities; in particular, if one has already paid for the interposer for the purposes of memory integration, any additional benefits from exploiting the interposer could come at a relatively small incremental cost. In this talk, I will describe the exciting opportunities enabled though interposer-based integration including our recent work on reduced manufacturing costs. I will also explore some of the key challenges associated with communicating data across chiplet boundaries through the interposer.

Biography
Natalie Enright Jerger is the Percy Edward Hart Professor of Electrical and Computer Engineering at the University of Toronto. Prior to joining the University of Toronto, she received her PhD from the University of Wisconsin-Madison in 2008. She received her Bachelor's degree from Purdue University in 2002. She is a recipient of the Ontario Ministry of Research and Innovation Early Researcher Award in 2012, the 2014 Ontario Professional Engineers Young Engineer Medal, and the 2015 Borg Early Career Award. She served as the program co-chair of the 7th Network-on-Chip Symposium and as the program chair of the 20th International Symposium on High Performance Computer Architecture. She is currently serving as the ACM SIGMICRO Vice Chair and an ACM SIGARCH Executive Committee member. Her current research explores on-chip networks, approximate computing, IoT architectures and machine learning acceleration. In 2017, she co-authored the second edition of the Computer Architecture Synthesis Lecture on On-Chip Networks with Li-Shiuan Peh and Tushar Krishna. She is passionate about increasing the representation of women in computing, particular in computer architecture. She currently chairs the organizing committee for the Women in Computer Architecture group (WICARCH).